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tv encoder CS8552 block diagram general description century semiconductor inc. features usa: 1485 saratoga ave. #200 san jose, ca, 95129 tel: 408-973-8388 fax: 408-973-9388 sales@century-semi.com sales@century-semi.com.tw www.century-semi.com rev.0.1 may 2001 page 1 of 23 century semiconductor, inc. taiwan: no. 2, industry east rd. 3rd, science-based industrial park, hsin-chu, taiwan tel: 886-3-5784866 fax: 886-3-5784349 CS8552 provides full conversion from digital video format ycbcr into ntsc/pal composite and s- video. it can be used in vcd, dvd, digital vcr application. two-times oversampling reduces the output filter requirements and guarantees no alias interference by internal uv filters and y filter. two 9-bit dacs provides two channels for a s- video output port or two composite video outputs with high quality of image. 32-pin package and pin assignment make CS8552 compatible with major vendors. ? designed special for vcd, karaoke, digital vcr, dvd, digital set-top box. ? support the following 4 modes: ntsc, pal-m, pal-bdghi, pal-nc ? 8-bit 4:2:2 ycbcr inputs for glueless interface to mpeg decoders ? cvbs (composite yc) or s-video (y and c) outputs ? support ccir-6-1 for mat, non-square pixel ? 2x oversampling simplify external filtering ? 6mhz and 1.3mhz anti-alias filters for y and u/v channels each ? on-chip color bar generation ? 2 channels of 9-bit dac ? support master and slave modes ? support interlace operation only ? automatic mode detection/switching in slave mode ? 3.3v supply voltage; 5v tolerant for all digital i/o pins video-timing controller sub-carrier generation sine-table serial to parallel 4:2:2 to 4:4:4 inter- u-filter v-filter y-filter polation h, v-sync clk_27 sleep p[7:0] mode[3:0] svideo master cbswap color-burst & modulation & mixer cvbs/y cvbs/c dac- mapping vbias vref_o fsadjust comp
CS8552 century semiconductor inc. page 2 of 23 pin connection diagram figure-1 32-pin plcc 30 31 32 1 2 3 4 CS8552 vss vdd vsync hsync nc vss cvbsy 20 19 18 17 16 15 14 md0 md1 md2 md3 masteri cbswapi svideoi 5 6 7 8 9 10 11 12 13 fadji compi vdd vrefo vrefi vbias cvbsc vss sleep clk_27m p7 p6 p5 p4 p3 p2 p1 p0 29 28 27 26 25 24 23 22 21
CS8552 century semiconductor inc. page 3 of 23 pin description name i/o pin description clki i 29 pixel clock, 27mhz, twice the y sample rate vsync i/o 32 vertical sync, output in master mode or input in slave mode, is synchronized by clk. hsync i/o 1 horizontal sync, output in master mode or input in slave mode, is synchronized by clk too. p[7:0] i 28-21 ycbcr pixel inputs (ttl compatible). also, synchronized by clk with respect to the incoming hsync timing, the higher index corresponds to a greater significance. md[3:0] i 17-20 configuration inputs master i 16 in 0: slave mode, h and v sync are inputs. 1: master mode, h and v sync are outputs. cbswap i 15 0: normal cr, cb sequence. 1: swaps cr, cb sequence svideo i 14 0: composite output same signal on both y, c channels, 1: s-video output, y, c channels. sleep i 13 1: power down, reset 0: normal operation fsadjust i 5 full scale adjust control pin. a resistor is connected to gnd. used to control the full-scale output current on analog outputs. comp i 6 compensation pin. a 0.1 f capacitor is used to bypass this pin to vcc. vrefo i 8 voltage reference output, typically 1.2v, may be used to connect to vrefi input. vrefi/vrdac i 9 voltage reference input, typically 1.235v. a 0.11 f capacitor must be used to decouple this input to gnd. dac current switch reference input, connect to vrefo output. vbias o 10 dac bias voltage, 0.7 v less than comp signal cvbs/c o 11 composite output or chrominance cvbs/y o 4 composite output or luminance (with blanking and sync) vaa 7 analog power vdd 31 digital power gnd 30 digital ground agnd 3, 12 analog ground nc 2 no connection
CS8552 century semiconductor inc. page 4 of 23 functional description mode configuration see table 1 to table 3 for details. master = 1: master mode horizontal sync and vertical sync are generated from internal timing and are output at the rising edge of clk_27. md[3]: define efield function 0: vsync is output pin 1: vsync is even/odd field indicator, vsync=0 even, vsync=1 odd. md[2]: define pal625 function 0: 525 line operation is set. 1: 626 line operation is set. master = 0: slave mode horizontal sync and vertical sync are inputs that are synchronized by clk_27. a falling edge of vsync* occurring within 1/4 of a scan line from the falling edge of hsync* cycle time indicates the beginning of field-1. a falling edge of vsync* occurring within 1/4 of a scan line from the middle point of the line indicates the beginning of field-2. see figure 2 figure-2 md[3]: define ycswap 0: normal operation. 1: swap the luma and chroma samples. md[2]: define setup function 0: 7.5 ire setup is enabled for ntsc and pal-m, with scaling for 92.5% black-to-white range, other pals with normal 100% black-to-white range. 1: 7.5 ire setup is disabled for ntsc and pal-m, with scaling for 100% black-to-white range. md[1]: define palsa function, south america. 0: normal operation. 1: pal-m used for brazil 525 lines operation. pal-nc used for argentina 625 lines operation. field-1 field-2
CS8552 century semiconductor inc. page 5 of 23 table-1 efield efield is used when configured as a master. when efield is set low, the normal vsync* signal is output on the vsync* pin. when efield is set high, field id information is output on the vsync* pin (vsync* low for field-1 and high for field-2) pal625 pal625 is used when configured as a master. when pal625 is set low, 525-line operation is selected. when pal625 is set high, 625-line operation is selected. this mode is set by automatic detection when configured as a slave. ycswap ycswap should normally be set to zero. when configured as a slave, this bit can be set high to swap the luma and chroma samples, thus altering the pixel sequence with respect to the incoming hsync* timing reference. setup setup is normally low for the common video modes. the setup and scaling function is toggled when this bit is high. when setup is low, the 7.5ire setup is enabled for ntsc and pal-m with scaling amplified for a 92.5% black-to-white range; other pal formats have setup disabled with normal 100% scaling. when setup is high, the 7.5 ire setup is disabled for ntsc and pal-m with 100% black-to-white range scaling; other pal formats have setup enabled with amplified scaling. palsa palsa is normally low for the common video modes. south american video standards can be enabled by setting this bit high. for 525-line operation, the palsa enables pal-m for brazil; in 625- line operation, the palsa enables pal-nc for argentina. table-2 master mode: table-3 slave mode: mode mode[3] mode[2] mode[1] mode[0] slave ycswap setup palsa reserved master efield pal625 reserved reserved master mode[3:0] system pal-625 palsa fv hz fh hz 1 x000 x010 (normal setup) ntsc 00 59.94 15734.26 1 x000 x010 pal-m 0 1 59.94 15734.26 1 x000 x110 pal-bdghi 1 0 50.00 15625 1 x010 x110 pal-nc 1 1 50.00 15625 master mode[3:0] system pal-625 palsa fv hz fh hz 0 x000 ntsc 0 0 59.94 15734.26 0 x010 pal-m 0 1 59.94 15734.26 0 x000 pal-bdghi 1 0 50.00 15625 0 x010 pal-nc 1 1 50.00 15625
CS8552 century semiconductor inc. page 6 of 23 pixel input/output timing 1. clk is 2x the luminance sampling rate (13.5 mhz) or 4x the chrominance sampling rate (6.75 mhz), all signals are reference to rising edge. 2. in accordance with ccir656, the input pixel pattern begins during the first clk period after the falling edge of hsync (same for master mode and slave mode). the input pattern is cb0, y0, cr0, y1, cb2, y2, cr2, y3,...... the input pin cbswap and md[3] (ycswap) could be used to swap cb, cr sequence and also y and cb, cr sequence. see figure 3 . 3. pixel input range: see table 4 y: 16-235 for normal range; 0-15, 236-255 are invalid. when y value is between 0-15 then clamp to 16, when 236 and 255 y will be set to 255. cbcr: 16-240 for normal range with 128 mapped to 0; 0-15, 241-255 are invalid. when cb/cr is between 0-15 will be clamp to 16, when cb/cr is 241 to 255 then will be set to 240. table-4 75% amplitude, 100% saturated ycbcr color bars figure-3 element range white yellow cyan green magenta red blue black y 16-235 235 162 131 112 84 65 35 16 cb 16-240 128 44 156 72 184 100 212 128 cr 16-240 128 142 44 58 198 212 114 128 clk hsync* ycswap=0 p[7:0]/cbswap=0 ycswap=1 p[7:0]/cbswap=1 p[7:0]/cbswap=0 cb0y0cr0y1cb2y2cr2y3cb4 cr0 y0 cb0 y1 cr2 y2 cb2 y3 cr4 y0 cb0 y1 cr2 y2 cb2 y3 cr4 y0 cr0 y1 cb1 y2 cr2 y3 cb4 y4 y4 p[7:0]/cbswap=1
CS8552 century semiconductor inc. page 7 of 23 video timing see table 5 , table 6 1. if master mode is selected, horizontal counter is incremented on clk/2, and reset to 1 when h-total is hit. the output hsync is 6 clk later than the internal horizontal sync. vertical counter is incremented by every horizontal scan line and reset to 1 after v-total hit. the output vertical sync is 3 or 2.5 lines for 262/525 and 312/625 later. 2. if slave mode is selected, the horizontal counter is incremented on the rising of clk and then reset to 1 after 2 clk cycles late of falling edge of hsync. the vertical counter is incremented on the falling edge of hsync and reset to 1 at falling edge of vertical sync. if the falling edge of vertical sync occurring within [-1/4,1/4] of a scan line from the falling edge of hsync indicates the even field, if within [-1/4,1/4] of middle point of scan line indicates odd field. 3. the width of horizontal sync and the start and end of color burst is automatically calculated and inserted for each mode. 4. sync timing and burst envelopes are internally controlled. color burst frequency is derived from the clk. any jitter on clk may induce a color burst frequency error. 5. timing tables: table-5 vertical timing table table-6 horizontal timing table: number of 13.5 mhz cycles 6. color burst is disabled on appropriate scan lines. serration and equalization pulses are generated on appropriate scan lines. for ntsc, color burst information is automatically disabled on scan line 1-9 and 264- 272 or pal-m, color burst information is automatically disabled on scan line 1-11 and 263-273. for pal- bdghinc, color burst information is automatically disabled on scan line 1-6 and 310-318 and 623-625 for field 1,2,5,6. however, for field 3,4,7,8 burst is disabled at scan line 1-5,311-319,622-625. see the following figure 4 , figure 5 and figure 6 . system odd-field non-active odd-field active even-field non-active even-field active total size active size ntsc line 1-22 vbi=7-21 line 23-262 line 263-284; 525 vbi=270-284 line 285-524 858*525 720*480 pal-bdk. line 1-22 vbi=7-21 line 23-310 line 311-335; 624, 625 vbi=319-333 line 336-623 864*625 720*576 system front-porch back-porch active burst-start burst-width total ntsc 20 127(122) 711 72 34 858 pal-m 20 127 711 78 34 858 pal-bd.. 20 142(132) 702 76 30 864 pal-nc 20 142 702 76 34 864
CS8552 century semiconductor inc. page 8 of 23 figure-4 interface 525-line (ntsc) video timing 262 263 264 265 266 267 268 269 270 271 272 273 1 525 2 3 4 5 6 7 8 9 10 analog field-2 analog field-3 burst phase 262 263 264 265 266 267 268 269 270 271 272 273 analog field-4 burst phase 1 525 23 4 5 6 78 9 10 start of vsync (equalization) (serration) (equalization) analog field-1 burst begins with positive half-cycle burst phase=reference phase=180 relative to b-y burst begins with negative half-cycle burst phase=reference phase=180 relative to b-y
CS8552 century semiconductor inc. page 9 of 23 figure-5 interface 625-line (pal-b,d,g,h,i,n,nc) video timing -u phase 623 622 624 625 1 2 3 4 5 6 7 analog field-1 burst phase=reference phase=135 relative to u; pal switch=0, +v component burst phase=reference phase + 90=225 relative to u; pal switch=1, -v component 621 start vsync analog field-2 309 310 311 312 313 314 315 316 317 318 319 320 analog field-3 623 622 624 625 1 2 3 4 5 6 7 621 analog field-4 309 310 311 312 313 314 315 316 317 318 319 320 field-1 field-2 field-3 field-4
CS8552 century semiconductor inc. page 10 of 23 figure-6 figure-6 figure-6 figure-6 -u phase 623 622 624 625 1 2 3 4 5 6 7 analog field-5 burst phase=reference phase = 135 relative to u; pal switch=0, +v component burst phase=reference phase + 90 = 225 relative to u; pal switch=1, -v component 621 start vsync analog field-6 309 310 311 312 313 314 315 316 317 318 319 320 analog field-7 623 622 624 625 1 2 3 4 5 6 7 621 analog field-8 309 310 311 312 313 314 315 316 317 318 319 320 field-5 field-6 field-7 field-8
CS8552 century semiconductor inc. page 11 of 23 anti-alias filters characteris the y and the u, v are up-samples to clk, 27mhz after 4:2:2 to 4:4:4 conversion. y is filtered by a filter whose passband is 6mhz. and u, v are also filtered by passband = 1.3mhz filters. please refer to figure 7 to figure 10 figure-7 2x sample y filter frequency response/passband figure-8 2x sample y filter frequency response/stopband db 0 -1 -3 -2 02468 mhz 0 -10 -20 -40 -55 db 02 4 68 10 mhz
CS8552 century semiconductor inc. page 12 of 23 figure-9 2x u/v filter frequency response/passband figure-10 2x u/v filter frequency response/stopband db 0 -1 -3 -2 02468 mhz 0 -10 -20 -40 -55 db 0 0.5 1 1.5 2 2.5 mhz
CS8552 century semiconductor inc. page 13 of 23 dac mapping depends on the video output mode, the color bars mapping to dac are specified in table 7 to table 12 and figure 11 to figure 16 . where white is 400. for pal-bdghinc blank = 120. for ntsc/pal-m blank = 114 (setup = 0), 1 ire = 2.857; if setup = 1, blank = 112, 1 ire = 2.8. table-7 s-video y ntsc/pal-m 525, setup = 0 figure-11 color bars, s-video y ntsc/pal-m 525, setup=0 video output waveform description dac data sync interval white 400 0 black 136 0 blank 114 0 sync 01 400 370 321 291 245 215 166 136 100 ire ma 26.68 1.000 v wycgmrb 114 blank level 7.5 ire 40 ire 9.07 7.6 0.285 0.34 0.00 0.00 sync level w: white y: yellow c: cyan g: green m: magenta r: red b: blue
CS8552 century semiconductor inc. page 14 of 23 table-8 s-video y pal-bdghinc 625 typical with 37.5 ? ? ? ? load, vref_o = vref_i, setup = 0 100% saturation (100/0/100/0) color bars. figure-12 color bars, s-video y pal-bdghinc 625 video output waveform description dac data sync interval white 400 0 black 120 0 blank 120 0 sync 01 400 368 319 284 236 204 152 ma 26.68 1.000 v wycgmrb 8.0 0.30 0.00 0.00 sync level w: white y: yellow c: cyan g: green m: magenta r: red b: blue black/blank level 120
CS8552 century semiconductor inc. page 15 of 23 table-9 s-video chrominance ntsc/pal-m 525 typical with 37.5 ? ? ? ? load, vref_o = vref_i, setup = 0 100% saturation color bars. figure-13 color bars, s-video chrominance ntsc/pal-m 525 video output waveform description dac data sync interval peak c (high) 423 no burst (high) 313 no blank 256 no burst (low) 199 no peak c (low) 89 no blank level color-burst 5.93 0.222 ma 28.21 1.058 v 20.88 17.07 0.64 0.783 13.27 0.498
CS8552 century semiconductor inc. page 16 of 23 table-10 s-video chrominance pal-bdgnicc 625 typical with 37.5 ? ? ? ? load, vref_o = vref_i, setup = 0 100% saturation (100/0/100/0) color bars. figure-14 color bars, s-video chrominance pal-bdgnicc video output waveform description dac data sync interval peak c (high) 433 no burst (high) 316 no blank 256 no burst (low) 196 no peak c (low) 79 no blank level color-burst 5.27 0.198 ma 28.88 1.083 v 21.08 17.07 0.64 0.791 13.07 0.490
CS8552 century semiconductor inc. page 17 of 23 table-11 composite ntsc/pal 525 typical with 37.5 ? ? ? ? load, vref_o = vref_i, setup = 0 100% saturation color bars. figure-15 colors, composite ntsc/pal 525 video output waveform description dac data sync interval peak c (high) 488 0 white 400 0 burst (high) 171 0 black 136 0 blank 114 0 burst (low) 57 0 peak c (low) 48 0 sync 01 blank level 3.8 0.143 ma 32.55 1.221 v 26.68 11.41 0.423 1.000 400 370 321 291 245 215 166 136 114 sync level 7.5 ire 20 ire 20 ire 40 ire 100 ire 9.07 0.34 7.6 0.285 0.00 0.00
CS8552 century semiconductor inc. page 18 of 23 table-12 composite pal-bdghinc 625 typical with 37.5 ? ? ? ? load, vref_o = vref_i, setup = 0 100% saturation (100/0/100/0) color bars. figure-16 colors, composite pal-bdghinc 625 video output waveform description dac data sync interval peak c (high) 488 0 white 400 0 burst (high) 171 0 black 136 0 blank 114 0 burst (low) 57 0 peak c (low) 48 0 sync 01 1.8 0.068 ma 32.88 1.233 v 26.68 12.01 0.45 1.000 400 368 319 284 236 204 152 sync level 8.0 0.30 4.0 0.15 0.00 0.00 120 black/blank level
CS8552 century semiconductor inc. page 19 of 23 recommended operating conditions absolute maximum ratings symbol parameter min typ max unit vaa power supply 3.0 3.3 3.6 v ta ambient operating temperature 0 - 70 c rl dac output load 37.5 -- ? vref_in external voltage reference 1.11 1.23 1.35 v nominal rest 850 ? symbol parameter min typ max unit vaa power supply (measured to ground) -- -- 5 v ta ambient operating temperature -55 -- 125 c voltage on any signal pin gnd-0.3 vaa+0.3 v ts storage temperature -65 +150 c tj junction temperature +150 c
CS8552 century semiconductor inc. page 20 of 23 dc characteristics (recommended operating conditions using external voltage reference with rset = 850 ?, vrefin = 1.23v, ntsc ccir601 operation and clock frequency = 27mhz at 25 c, +3.3v) symbol parameter min typ max unit iaa vaa supply current 105 ma video d/a resolution 9 9 9 bits inl integral nonlinearity 1 lsb dnl differential nonlinearity 1 lsb maximum output current 35 ma voc output compliance 0 1.5 v video level error 5 % full-scale dac output 182.5 ire digital inputs input high voltage input low voltage input high current (vin=2.4v) input low current (vin=0.4v) vih 2.0 vaa+0.3 v vil gnd-0.3 0.8 v iih 1 a iil -1 a digital outputs output high voltage (ioh=-400 a) output low voltage (iol=3.2ma) three-state current voh 2.4 v vol 0.4 v ioz 50 a vref_in vref_in input current 10 a vref_out vref_out output voltage 1.11 1.23 1.35 v iref_out vref_out current 10 a
CS8552 century semiconductor inc. page 21 of 23 ac characteristics (recommended operating conditions using external voltage reference with rset = 850 ?, vrefin = 1.23v, ntsc ccir601 operation and clock frequency = 27mhz at 25 c, +3.3v) symbol parameter min typ max unit luminance bandwidth f ck /4 mhz chrominance bandwidth 1.3 mhz differential gain 1 % differential phase 1 snr 60 db hue accuracy 1.5 3 color saturation accuracy 1.5 3 % 4 analog output delay 30 ns analog output rise time 3 ns analog output setting time 30 ns 1 pixel/control setup time 1 ns 2 pixel/control hold time 3 ns 3 control output delay time 15 ns f ck clock frequency 24.54 27 29.5 mhz clock pulse width low time 10 ns clock pulse width high time 10 ns
CS8552 century semiconductor inc. page 22 of 23 video input and output timing figure-17 video input and output timing (master mode) pixel 0 pixel 1 12 3 pixel 0 pixel 1 4 clock p[7:0] hsyncn, vsyncn analog output hsyncn, vsyncn (slave mode)
CS8552 century semiconductor inc. page 23 of 23 package outline (32-pin plcc) symbol dimensions in millimeters dimensions in inches min nom max min nom max a - - 3.56 - - 0.14 a1 0.50 - - 0.020 - - a2 2.79 ref 0.110 ref a3 0.20 - 0.35 0.008 - 0.014 a4 1.91 2.29 2.41 0.075 0.090 0.095 b 0.40 - 0.53 0.016 - 0.021 b1 0.66 - 0.81 0.026 - 0.032 d 12.32 12.45 12.57 0.485 0.490 0.495 d1 11.35 11.43 11.51 0.447 0.450 0.453 d2 5.21 ref 0.205 ref e 14.86 14.99 15.11 0.585 0.590 0.595 e1 13.89 13.97 14.05 0.547 0.550 0.553 e2 6.48 ref 0.255 ref e 1.27 ref 0.050 ref 0?100?10 a2 a d d1 identifier 5 13 14 20 21 29 4 1 32 30 pin 1 e1 e b1 e b d2 d2 a1 e2 e2 a3 a4

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